The present invention relates generally to memory, and more specifically, to using a flash device as a cache memory.
Flash memory devices are a type of non-volatile storage devices that can be electrically erased and reprogrammed in large blocks. Flash memory devices store information in an array of memory cells made from floating-gate transistors. Single-level cell (SLC) flash memory devices store one bit of information in each cell. Multi-level cell (MLC) flash memory devices can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells. Flash memory devices have a limited lifetime because they can only support a finite number of program-erase (P/E) cycles. Contemporary commercially available flash memory devices are typically guaranteed to support a specified number of P/E cycles before the wear begins to impact the reliability of the storage.
Using flash memory devices as an alternative or supplement to dynamic random access memory (DRAM) and/or to hard disk drives (HDDs) is becoming increasingly attractive as the cost of flash memory decreases and the performance of flash memory increases. From a cost perspective, flash memory is currently about ten times less expensive than conventional DRAM. The lower cost of flash memory allows much larger data sets to be stored without a corresponding increase in the cost of the memory. From a performance perspective, contemporary flash memories currently have about two orders of magnitude higher random read throughput than traditional mechanical drives. One downside to the use of flash memory devices for cache memory is that flash memory devices have a limited life and may not be ideal for storing data subject to a large number of updates.